1. Field of the Invention
This invention relates generally to processors and, more specifically, to a processor architecture scheme and instruction set which will allow for maximizing the number of available opcodes and for the encoding of multiple addressing modes through virtual register addresses to maximize the number of directly addressable registers in the processor architecture scheme.
2. Description of the Prior Art
Generally speaking, a processor is an entity where a central processing unit (CPU) is present and is used to fetch and execute stored instructions or micro-code. Some examples of processors are microcontrollers, microprocessors, and digital signal processors. Each type of processor operates on data which is also commonly referred to as operands. This data is generally stored in registers or memory space.
An instruction directs the CPU of a processor to execute a certain operation as well as to identify one or more operand(s) for the operation. Processors offer various means for addressing the data for an operation. These means are commonly referred to as addressing modes. The addressing modes are typically used for arithmetic and logical operations and data move operations and may apply to a source operand, a destination operand, or both.
The problem with current processor architecture schemes is that adding or changing addressing modes is extremely difficult. Without major changes to the instruction set organization, such changes and additions to the addressing modes are not possible. However, changes to the instruction set structure is not desirable since many tools such as assemblers and compilers will also require dramatic changes.
One way to implement different addressing modes is to dedicate bits in the opcode field or the register address field. By setting the dedicated bits, different addressing modes can be implemented. The problem with these architecture schemes is that the number of available opcodes or the number of directly addressable "registers" diminishies significantly. For example, if 8-bits of an instruction are used to encode the "op-code", if two bits of the "op-code" are used to determine the addressing mode, the total number of available instructions decreases from 256 to 64. On the other hand, if 8-bits are available in an instruction word to specify a register operand, it would be possible to address 256 registers directly. However, in order to incorporate other addressing modes, if one of the 8-bits is taken away for this purpose, only 128 registers can now be directly addressed.
In existing processor architecture schemes, where alternate addressing modes are available, encoding is implemented through "control registers" in order to maximize the number of directly addressable registers. However, this creates yet another problem since "selection" of indirect addressing modes is static (until reconfigured) and not dynamic from instruction to instruction.
Therefore, a need existed to provide an improved microcontroller architecture scheme. The improved microcontroller architecture scheme must allow the user to add and change addressing modes. The improved microcontroller architecture scheme must further allow the user to change addressing modes dynamically on an instruction by instruction basis. The improved microcontroller architecture scheme must allow the user to add and change addressing modes while maximizing the number of available opcodes for a given number of instruction bits. The improved microcontroller architecture scheme must further allow the user to add and change addressing modes while maximizing the number of directly addressable registers.